1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and a display device having the semiconductor device.
2. Description of the Related Art
Thin film transistors (hereinafter, referred to as TFTs) have been known as a semiconductor device. TFTs are used preferably to drive display devices such as a liquid crystal display device and an organic EL display device.
Especially a-Si TFTs having a channel region made of only an amorphous film such as amorphous silicon (a-Si) have been most commonly used in the industry. A so-called channel etch type TFT (Conventional structure 1) will now be described with reference to an enlarged cross-sectional view of FIG. 17. A TFT 100 has a gate electrode 102 formed on a substrate 101, a gate insulating film 103 covering the gate electrode 102, an a-Si layer 104 formed on the gate insulating film 103 to form a channel region, a source region 105 and a drain region 106 which are made of an n+-Si layer patterned on the a-Si layer 104, a source electrode 107 covering the source region 105, and a drain electrode 108 covering the drain region 106.
Since the channel region is made of an amorphous film, the a-Si TFT of Conventional structure 1 has a mobility of about 0.2 to 0.5 cm2/Vs and has relatively poor on-state characteristics. On the other hand, since the gate insulating film is made of a silicon nitride film, the gate insulating film has excellent interface characteristics with the a-Si layer 104 of the channel region, thereby improving the rising characteristics (S value) of an on-state current. Moreover, the a-Si layer 104 has a wide bandgap and therefore a leakage current (off-state current) is small. A leakage current is reduced also at the interface between the a-Si layer 104 and the source region 105 and the drain region 106.
A TFT (Conventional structure 2) having a channel region made of only a film having a crystal layer (microcrystalline silicon film) is also known in the art. The TFT has the same structure as that of the above a-Si TFT except that the channel region is made of a microcrystalline silicon film and the gate insulating film is made of a silicon nitride film or a silicon oxide film. Since the channel region has a crystalline property, this TFT has a mobility of 1 to 3 cm2/Vs and has improved on-state characteristics.
However, since the microcrystalline silicon film (the channel region) has a multiplicity of defect levels, the microcrystalline silicon film has poor characteristics at a junction interface with the n+-Si layer (the source region and the drain region). In other words, the microcrystalline silicon film has a lower electric resistance and a narrower bandgap than the a-Si layer, and therefore has a larger off-state current than the a-Si layer.
Moreover, the microcrystalline silicon film (the channel region) has a mixed structure of crystalline silicon and amorphous silicon. Accordingly, an excellent interface cannot be obtained regardless of whether the gate insulating film is made of a silicon oxide film or a silicon nitride film. In other words, a fixed charge density and an interface state density become extremely high, and an extreme negative shift of the TFT threshold voltage and degradation in S value will become a problem. Moreover, since the manufacturing process becomes very unstable, it is difficult to control the threshold voltage.
Hereinafter, the TFTs of Conventional structures 1 and 2 will be described with reference to a graph of voltage-current characteristics shown in FIG. 19. Solid line in FIG. 19 indicates a change in current value with increase in applied voltage in the TFT of Conventional structure 1 (the channel region is an a-Si layer and the gate insulating film is SiNx). When the applied voltage is in the range of −40 to −10 V, the current value varies significantly at about 10−12 A or less. When the applied voltage becomes higher than −10 V, an on-state current rises and increases rapidly. As can be seen from the graph, the on-state current then asymptotically increases to about 10−2 A with increase in applied voltage.
Similarly, chain line in FIG. 19 indicates a change in current value with increase in applied voltage in the TFT of Conventional structure 2 (the channel region is a microcrystalline silicon layer and the gate insulating film is SiNx). The current value decreases monotonously when the applied voltage is in the range of −40 to −22 V. As can be seen from the figure, with increase in applied voltage, the current value then increases and an on-state current rises and asymptotically increases to about 10−2 A.
Similarly, dashed line in FIG. 19 indicates a change in current value with increase in applied voltage in the TFT of Conventional structure 2 (the channel region is a microcrystalline silicon layer and the gate insulating film is SiOx). The current value decreases monotonously when the applied voltage is in the range of −40 to −25 V. With increase in applied voltage, an on-state current rises and asymptotically increases to about 10−3 A.
It can therefore be seen that, in Conventional structure 2, an off-state current increases and rising characteristics of the current are inferior to those of Conventional structure 1 regardless of whether the gate insulating film is SiNx or SiOx.
As shown in a cross-sectional view of FIG. 18, it is known in the art to interpose the a-Si layer 104 between a microcrystalline silicon layer 110 and the source region 105 or the drain region 106 (e.g., see Patent documents 1 and 2). In other words, the microcrystalline silicon layer 110 is formed on the gate insulating film 103, and the a-Si layer 104 is formed on the microcrystalline silicon layer 110. The source region 105 and the drain region 106 are thus formed on the a-Si layer 104. This structure tries to solve the problem of Conventional structure 1, that is, a low mobility in the channel region.
Patent document 1: Japanese Laid-Open Patent Publication No. S62-295465
Patent document 2: Japanese Laid-Open Patent Publication No. 2001-217424